1. Technical Field
The present invention relates to analog-digital converters, in particular to successive approximation register (SAR) analog-digital converters (ADCs) and measures to increase the accuracy thereof while maintaining conversion speed and power consumption.
2. Description of the Related Art
SAR converters for analog-digital conversion are well known in the art. In particular, SAR converters are frequently used in integrated CMOS devices since they provide a reasonable resolution and conversion time and can be implemented by optimally utilizing the advantages of the CMOS technology, which are small-sized switches and capacitors having relatively well-defined relative capacitances.
Although SAR ADCs can be implemented in different topologies, they generally include at least one capacitor array. The capacitor array may include a unit capacitor array with stages of identical capacitances and one stage with a doubled capacitance, or a capacitance ladder network comprising stages with capacitance values in a mutual relation of a factor of 2n (n=number of stages).
The capacitors, of the capacitor, array may be charged by connecting to a signal line carrying an input signal potential to be converted. The capacitor array is connected to a latch/comparator which serves for comparing a potential, stored in the capacitor array, to a reference potential in a sampling phase. The comparison result is stored in a shift register. Based on the comparison result of the previous comparing phase, a switching of a capacitance of the capacitor array is performed to increase or decrease the potential stored in the capacitor array before a next comparison is performed. This is repeated until all stages of the capacitor array have been processed.
SAR ADCs generally rely on a capacitor array, including integrated capacitors having well-defined relative capacitances. However, the capacitances of the integrated capacitor array are prone to have a remaining relative mismatch due to the commonly used CMOS technology, e.g., due to lithography, which might result in a higher integral and differential nonlinearity. The matching accuracy of the capacitors strongly depends on their size, such that the higher the areas of the matched capacitors the lower the matching error. In general, the matching error of the capacitors is determined to be no less than an ADC resolution error. Implementing the capacitor array with an intrinsic matching of the capacitors (determined by the area use of the capacitors) beyond the required resolution is, therefore, inefficient with respect to area and power consumption.
Document U.S. Pat. No. 8,223,044 B2 discloses an SAR ADC in which correction capacitors are provided to correct an integral nonlinearity error. The correction capacitors are coupled with a certain comparator depending on stored integral nonlinearity error information, wherein the correction capacitors are selectively coupled to either a ground voltage or a reference voltage.
Document U.S. Pat. No. 7,944,379 B2 discloses an apparatus for analog-to-digital conversion using successive approximation, wherein an integral nonlinearity compensator is configured to provide an integral nonlinearity compensation signal for reducing the integral nonlinearity of the analog-to-digital conversion in response to the digital code representing a conversion result.
Document U.S. Pat. No. 7,280,063 B2 discloses an SAR digital-to-analog converter with an operational amplifier and a plurality of ladder elements of a ladder network. Each ladder element includes a tunable voltage source for providing a voltage, a capacitor, and a switch for selecting a first voltage or a reference voltage and for providing the first selected voltage to the first capacitor. The output of the ladder elements is coupled to the inverting input of the operational amplifier. The reference voltages can be programmed to minimize a mismatch between the capacitors.
Document V. Kerzérho et al., “Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter”, IEEE Transactions on Instrumentation and Measurement, Vol. 60, Issue 3, March 2011, discloses an SAR ADC converter using a look-up table for the online correction of integral nonlinearity.
Furthermore, document U. Moon et al., “A Switched Capacitor DAC with Analog Mismatch Correction”, Electronics Letters, Vol. 35, Issue 22, Oct. 28, 1999, discloses a calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter.